46 lines
1.2 KiB
Diff
46 lines
1.2 KiB
Diff
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--- a/drivers/gpu/drm/panel/panel-cwu50.c
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+++ b/drivers/gpu/drm/panel/panel-cwu50.c
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@@ -27,12 +27,12 @@ static const struct drm_display_mode default_mode = {
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.clock = 61020,
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- .hdisplay = 1280,
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- .hsync_start = 1280 + 8,
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- .hsync_end = 1280 + 8 + 2,
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- .htotal = 1280 + 8 + 2 + 16,
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- .vdisplay = 720,
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- .vsync_start = 720 + 30,
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- .vsync_end = 720 + 30 + 15,
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- .vtotal = 720 + 30 + 15 + 15,
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+ .hdisplay = 720,
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+ .hsync_start = 720 + 30,
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+ .hsync_end = 720 + 30 + 15,
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+ .htotal = 720 + 30 + 15 + 15,
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+ .vdisplay = 1280,
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+ .vsync_start = 1280 + 8,
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+ .vsync_end = 1280 + 8 + 2,
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+ .vtotal = 1280 + 8 + 2 + 16,
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};
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static inline struct cwu50 *panel_to_cwu50(struct drm_panel *panel)
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@@ -586,7 +586,8 @@ static int cwu50_init_sequence2(struct cwu50 *ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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- int err;
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+ int err;
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+ u8 buf[4];
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dcs_write_seq(0xE0,0x00);
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@@ -633,6 +634,12 @@ static int cwu50_init_sequence2(struct cwu50 *ctx)
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dcs_write_seq(0x11);// SLPOUT
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msleep (200);
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+ dcs_write_seq(0xE0,0x00);
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+ mipi_dsi_dcs_read(dsi, 0x04, buf, 3);
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+
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+ if(buf[0] == 0x39) ctx->is_new_panel = 1;
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+
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+ dcs_write_seq(0xE0,0x00);
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dcs_write_seq(0x29);// DSiPON
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msleep (100);
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