--- a/drivers/gpu/drm/panel/panel-cwu50.c
+++ b/drivers/gpu/drm/panel/panel-cwu50.c
@@ -27,12 +27,12 @@ static const struct drm_display_mode default_mode = {
 	.clock = 61020,
-	.hdisplay = 1280,
-	.hsync_start = 1280 + 8,
-	.hsync_end = 1280 + 8 + 2,
-	.htotal = 1280 + 8 + 2 + 16,
-	.vdisplay = 720,
-	.vsync_start = 720 + 30,
-	.vsync_end = 720 + 30 + 15,
-	.vtotal = 720 + 30 + 15 + 15,
+	.hdisplay = 720,
+	.hsync_start = 720 + 30,
+	.hsync_end = 720 + 30 + 15,
+	.htotal = 720 + 30 + 15 + 15,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 8,
+	.vsync_end = 1280 + 8 + 2,
+	.vtotal = 1280 + 8 + 2 + 16,
 };
 
 static inline struct cwu50 *panel_to_cwu50(struct drm_panel *panel)
@@ -586,7 +586,8 @@ static int cwu50_init_sequence2(struct cwu50 *ctx)
 {
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-	int err;
+	int err;
+	u8 buf[4];
 
 	dcs_write_seq(0xE0,0x00);
 
@@ -633,6 +634,12 @@ static int cwu50_init_sequence2(struct cwu50 *ctx)
 
 	dcs_write_seq(0x11);// SLPOUT
 	msleep (200);
+	dcs_write_seq(0xE0,0x00);
+	mipi_dsi_dcs_read(dsi, 0x04, buf, 3);
+
+	if(buf[0] == 0x39) ctx->is_new_panel = 1;
+
+	dcs_write_seq(0xE0,0x00);
 
 	dcs_write_seq(0x29);// DSiPON
 	msleep (100);